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Document Reference No.: FT_000164
V2DIP2-32 VNCL2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 151
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3.5 Serial Peripheral Interface (SPI)
The VNC2-32Q has one master module and two slave modules. These modules are described more fully in
a VNC2 datasheet please refer to:-
3.5.1 Signal Description - SPI Slave
The SPI Slave signals can be programmed to a choice of available I/O pins. Table 3.4 explains the
available pins for each of the SPI Slave signals.
Available Pins
Name
Type
Description
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
spi_s0_clk
spi_s1_clk
spi_s0_mosi
spi_s1_mosi
spi_s0_miso
spi_s1_miso
spi_s0_ss#
spi_s1_ss#
Input
Input/Output
Output
Input
Slave clock input
Master Out Slave In
Synchronous data from master to
slave
Master In Slave Out
Synchronous data from slave to
master
Slave chip select
Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave
3.5.2 Signal Description - SPI Master
The SPI Master signals can be programmed to a choice of available I/O pins. Table 3.5 shows the SPI
master signals and the available pins that they can be mapped.
Available Pins
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
Name
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss_0#
Type
Output
Output
Input
Output
Description
SPI master clock input
Master Out Slave In
Synchronous data from master to
slave
Master In Slave Out
Synchronous data from slave to
master
Active low slave select 0 from master
to
slave 0
J2-10, J1-6, J1-11
spi_m_ss_1#
Output
Active low slave select 1 from master
to
slave 1
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master
Copyright ? 2010 Future Technology Devices International Limited
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